At its 2023 North American Technology Symposium today, TSMC has disclosed additional details about its plans for its forthcoming N2 2nm-class production nodes in 2025 – 2026 and beyond. TSMC’s N2 family of fabrication technologies will be expanding with additional variations, including N2P with backside power delivery, and N2X for high-performance computing. Between these forthcoming N2 generation process nodes, TSMC is laying out a roadmap to continue their relentless pace of increasing transistor performance efficiency, optimize power consumption, and improving transistor density.
N2 Gets Denser
TSMC’s initial N2 manufacturing process, which was introduced last year, will be the foundry’s first node to use gate-all-around (GAAFET) transistors, which TSMC is calling Nanosheet transistors. GAAFET’s advantages over current FinFET transistors includes lowered leakage current (as gates are present on all four sides of the channel), as well as the ability to adjust channel width for higher performance or lower power consumption.
When introducing this technology last year, TSMC said that it would enhance transistor performance by 10% to 15% with the same power and complexity, or reduce power consumption by 25% to 30% at the same clock and transistor count. The company also says that N2 will offer ‘mixed’ chip densities of over 15% greater than N3E, which is an increase from the 10% density increase announced last year.
Today, the company said that N2 technology development is on track and the node will enter high-volume production in 2025 (probably very late 2025). The company also said that its Nanosheet GAA transistor performance is achieving better than 80% of its target specifications two years before entering HVM, and that average yield of a 256Mb SRAM test IC is over 50%.
“TSMC nanosheet technology demonstrated excellent power efficiency and lower Vmin, best fit for energy-efficient compute paradigm,” a statement by TSMC reads.
|Advertised PPA Improvements of New Process Technologies
Data announced during conference calls, events, press briefings and press releases
|Q2 2022||H2 2022||Q2/Q3 2023||H2 2025|
*Chip density published by TSMC reflects ‘mixed’ chip density consisting of 50% logic, 30% SRAM, and 20% analog.
N2P Gets Backside Power Delivery In 2026
TSMC’s N2 family will evolve and sometime in 2026, when the company plans to introduce its N2P fabrication technology. N2P that will add backside power rails to N2’s Nanosheet GAA transistors.
Backside power delivery is meant to decouple I/O and power wiring by moving power rails to the back, addressing challenges like elevated via resistances in the back-end-of-line (BEOL). This, in turn, will enhance transistor performance and reduce their power consumption. Also, backside power deliver eliminates some potential interference between data and power connections.
Backside power delivery is innovation whose importance is hard to overstate. Chipmakers have been fighting resistances in chip power delivery circuitry for years, and backside power delivery networks (PDN) are a yet another method to address them. In addition, decoupling PDN and data connections also helps with area reduction, so expect N2P to further increase transistor density compared to N2.
For now, TSMC is not disclosing any hard numbers regarding N2P’s performance, power, and area (PPA) advantages over N2. But based on what we hear from industry sources, backside power rails alone could bring a single digit power improvements and double-digit transistor density improvements.
TSMC says that N2P is on track to be production ready in 2026, so we can speculate that the first N2P-based chips will be available in 2027. This timeline would put TSMC roughly two years behind rival Intel when it comes to backside power, assuming they’re able to ship their own 20A process on time in 2024.
N2X: Even More Performance
In addition to N2P, which will likely be a working horse of TSMC’s 2nm generation of processes, TSMC is also prepping N2X. This will be a fabrication process tailored for high-performance computing (HPC) applications like high-end CPUs, which need increased voltages and clocks. The foundry is not outlining the specific advantages this node will compared to N2, N2P, and N3X, but as with all performance-enhanced nodes, the actual benefits are expected to depend signficantly on how much design technology co-optimization (DTCO) is practiced.